Photonic Layout Engineer
This role involves designing and laying out photonic integrated circuits (PICs) for quantum processor units (QPUs) using Python-based tools. The engineer will collaborate with cross-functional teams to integrate photonic components into multi-layer chips, perform layout verification (DRC/LVS), and contribute to custom Process Design Kits (PDKs) for tape-out in commercial foundries. The work directly supports scaling trapped-ion quantum systems through on-chip photonics.