Senior Digital Design Engineer
Boston, MA, US | Full-time | Permanent | Hybrid
Salary: $142,000 to $170,000 DOE + Bonus + Benefits
About us
Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion.
Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.
About the role
We have a fantastic opportunity for an experienced Senior level Digital Design Engineer to join us as we build the world’s first quantum error correction (QEC) stack. Don’t have a background in quantum computing? Not a problem! This cutting-edge technology requires a wide range of skills and disciplines, including classical computing skills. You will learn quantum computing along the way.
As Senior Digital Design Engineer at Riverlane, you will help develop our decoder IP, at the heart of our QEC Stack. You will use your knowledge and expertise to support more junior engineers, interact with software and identify novel solutions to our challenging problems.
Our mission is exciting, but complex. It requires teams with a wide range of skills and perspectives, that communicate well and collaborate effectively to achieve truly innovative solutions.
You will thrive in an environment where knowledge sharing, and continuous learning are the norm. We are moving fast in a brand new market, where requirements can change as the technology evolves, so the ability to adapt is important.
What you will do
As a Senior Digital Design Engineer at Riverlane, you will work on one of these key areas:
- Implementation of QEC decoders on hardware;
- Implementation of low-latency, high throughput data movement between cards and IPs; or
- Design of low-latency interfaces to bring data in the systems.
- Mentor junior engineers (not a manager role-no direct reports)
In all of the above, you will (often from scratch) design end to end or integrate complex IPs and develop tests, collaborating closely with our Software, Verification and Testing experts to deliver an outstanding product.
What we need
- 5+ years of end to end design experience with complex, state-of-the-art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10)
- Experience with ASIC environments (<48nm) a plus
- Experience mentoring junior hardware design engineers
- Proven professional experience in at least one of the following areas:
- Customization of RISC-V CPUs e.g. addition of new instructions and associated hardware accelerators;
- Implementation of modern classical decoders on FPGA/ASIC e.g. LDPC, turbo-codes;
- Implementation of high-speed serial communication links across multiple FPGAs, or PCIe-based communication links
- Implementation of quantum control systems, or quantum decoders
- Architecture of System on Chip (SoC) solutions, with at least one CPU and custom accelerators
- Proven capability to test, debug and improve complex systems
- Ability to convert product requirements into technical specifications to document and share your work
- A curious nature and a passion for learning and continuous improvement
- Excellent communication skills, with the ability to work both independently and collaboratively as part of a team
What can you expect from us
- A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and 401K contributions
- Equity, so that our team can share in the long-term success of Riverlane
- Generous paid time off and enhanced family leave
- A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and math) and over 20 different nationalities
- A learning environment that encourages individual, team and company growth and development, including a regular program of learning events and training and conference budgets
How to apply
Please upload your resume and covering letter by clicking 'Apply'. Your cover letter should explain why you are applying for the job and what skills and experience you can bring to the role.
We review CVs as we receive them and interview as soon as we have applications that look like a good match. We do not use closing dates. Please apply as soon as possible to avoid missing out on this role.
If you have any queries, please contact jobs@riverlane.com.
Everyone is welcome at Riverlane. We are an equal opportunity employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.
Women and other underrepresented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements. If this applies to you, we still encourage you to apply - you may be a great fit, even if you don’t meet every single qualification. We’d love to hear from you.
If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.
GDPR notice: Riverlane collects and processes personal data in accordance with applicable data protection laws. If you are a European Job Applicant see the privacy notice for further details. #LI-CA
:quality(80))
:quality(80))
:quality(80)){kind=logo}